Data size and functionality requirements for computing are increasing, according to the expectation that hardware performance will continue to improve, irrespective of the actual implementation. However, the end of conventional technological roadmap scaling is anticipated in just a few technology nodes, mainly for cost reasons (multiple patterning, EUV) down to the 7nm FinFET gate length node. In this context, vertical integration is a particularly attractive approach because of its intrinsic 3D nature. The vertical NW (nanowire) array based transistor is a viable option to circumvent both physical and design limitations while they are much easier to manufacture. Therefore, new 3D logic architectures are mandatory.
The candidate to this position, available at the IMS Laboratory (UMR 5218 / University of Bordeaux), is required to work on different types of measurement and simulation using dedicated softwares and instruments:
- Electromagnetic simulations (Ansys HFSS and Keysight ADS-Momentum) to design and analyze dedicated de-embedding test structures
- Use of Vectorial Network Analyzer (VNA) for on-wafer measurements, involving probe-tip calibration and device S-parameter measurements (Keysight IC-CAP)
- SPICE/VerilogA simulation for compact model parameter extraction using on-wafer measurement data of
vertical nanowire transistors
- Possible interfacing with physical simulation using « Device Simulation Tools » for physical and electro-thermal simulation of vertical nanowire structures (Global TCAD Solutions softwares)
More details in this document.
- Prof. Cristell MANEUX